1. Field of the Invention
The present invention relates generally to systems and methods of comparing two or more dynamic nodes, and more particularly, to systems and methods for minimizing noise on dynamic nodes.
2. Description of the Related Art
A dynamic node is a logic signal line that is connected to one or more, and typically many, dynamic components and circuits. Typically a sensing circuit is connected to a dynamic node to detect the logical level present on the dynamic node. However, due to various dynamic changes occurring in the dynamic components and even in the sensing circuit, a noise signal can be superimposed on the logic level that is present on the dynamic node. Unfortunately, if the noise signal is allowed to become too large, the actual logic level that may be sensed by the sensing circuit can be affected. By way of example, if the noise signal becomes too large, then a logical zero (i.e., a logical low) that is supposed to be on the dynamic node can be sensed as a voltage greater than zero and therefore interpreted as a logical one (i.e., a logical high). Often times, a single sensing circuit compares two dynamic nodes. The noise signal can interfere with the accurate sensing of one or both of the respective logic levels present on the two dynamic nodes.
Many high performance microprocessors include one or more CAM (comparable address memory) cells. The CAM is used, for example, to compare stored data in memory with incoming address data. A CAM cell includes a memory and one or more a comparison device(s). The memory portion includes a SRAM cell and the comparison device includes multiple NMOS devices. The drain of the comparison devices is coupled to the match line. A local match line can be connected to multiple, nearby CAM cells. Typically, many NMOS devices are connected to the local match line. A PMOS, pre-charge device is also typically coupled to the local match line. PMOS, keeper device is also typically coupled to the local match line. The keeper device protects the local match line from being discharged by the NMOS devices in the CAM cells that are attached to the local match line. A sense amplifier is also coupled to the local match line. The sense amplifier senses the status of the local match line. The sense amplifier typically includes a two input NAND gate. However, back-gate coupling from the two input NAND gate can bias the PMOS keeper device. The constant “ON” status of the PMOS keeper device provides a DC current path that can increase the total current flow on the local match line.
FIG. 1A is a block diagram of a typical hierarchical CAM circuit 100. The hierarchical CAM circuit 100 includes multiple sets of CAM cells 102A, 102B, 104A, 104B, 106A, 106B, 108A and 108B. The sets of CAM cells 102A, 102B, 104A, 104B, 106A, 106B, 108A and 108B each have a respective, local match line 112A, 112B, 114A, 114B, 116A, 116B, 118A and 118B. Each of the local match lines 112A, 112B, 114A, 114B, 116A, 116B, 118A and 118B are a dynamic node that conducts the logic levels being output by the respective set of CAM cells 102A, 102B, 104A, 104B, 106A, 106B, 108A and 108B. By way of example, a first set of CAM cells 102A has a local match line 112A. Similarly, a second set of CAM cells 102B has a local match lines 112B.
A sensing and comparison circuit 122, 124, 126 and 128 are coupled to each respective pair of local match lines 112A, 112B, 114A, 114B, 116A, 116B, 118A and 118B. By way of example, comparison circuit 122 is coupled to local match lines 112A and 112B so as to be able to sense and compare the logic levels on the local match lines. Typically the sensing and comparison circuits 122, 124, 126 and 128 are NAND gates.
Each of the local match lines 112A, 112B, 114A, 114B, 116A, 116B, 118A and 118B are also coupled to respective pre-charge circuits 132A, 132B, 134A, 134B, 136A, 136B, 138A and 138B. The pre-charge circuits 132A, 132B, 134A, 134B, 136A, 136B, 138A and 138B maintain the logic levels on the respective local match lines 112A, 112B, 114A, 114B, 116A, 116B, 118A and 118B so that the respective CAM cells 102A, 102B, 104A, 104B, 106A, 106B, 108A and 108B do not have to sink or source the current required to charge or discharge the local match lines.
FIG. 1B is a more detailed block diagram the sensing circuit 122 and pre-charge circuits 132A and 132B. Each of the local match lines 112A and 112B also has a respective keeper circuit 142A and 142B. The keeper circuits 142A and 142B maintain the logic level of the respective local match lines 112A and 112B at the logic level applied to the local match lines by the respective sets of CAM cells 102A and 102B. Each of the keeper circuits 142A and 142B include a PMOS device with a grounded gate. This configuration of the keeper circuits 142A and 142B is referred to as a grounded gate keeper circuit.
FIG. 1C is another more detailed block diagram the sensing circuit 122 and pre-charge circuits 132A and 132B. Each of the local match lines 112A and 112B also has a respective keeper circuit 142A′ and 142B′. The keeper circuits 142A′ and 142B′ maintain the logic level of the respective local match lines 112A and 112B at the logic level applied to the local match lines by the respective sets of CAM cells 102A and 102B. Each of the keeper circuits 142A′ and 142B′ include a PMOS device with a gate coupled to the output of the sensing circuit 122. This configuration of the keeper circuits 142A′ and 142B′ is referred to as a feedback gate keeper circuit.
The different configuration of the gate circuits of the keeper circuits 142A, 142B, 142A′ and 142B′ yield different performance profiles. FIG. 1D is a graph of the gate voltage waveforms 150A and 150B respectively for the grounded gate keeper circuit and the feedback gate keeper circuit. The voltage on the respective match lines 112A and 112B are represented in graphs 152A and 152B. FIG. 1E is a graph of the drain to source current waveforms 160A and 160B respectively for the grounded gate keeper circuit and the feedback gate keeper circuit. Referring now to FIG. 1D, the gate voltage on the grounded gate keeper circuit incurs a slight increase 154 (e.g., to about 1.45v) coincident with a switching of states on the match line. However, this voltage increase is quickly reduced to the nominal voltage level of the match line (e.g., about 1.25v). In contrast, the gate voltage on the feedback gate keeper circuit also incurs the slight increase 154 but remains at the elevated voltage level (e.g., about 1.45v) until about time 156 when the match line voltage next switches states.
The increased gate voltage on the feedback gate keeper circuit is caused by the backgate coupling from the NAND gate 122. The backgate coupling is undesirable as it increases the leakage current of the feedback gate keeper circuits 142A′ and 142B′. As device sizes have become ever smaller, the backgate coupling is increased causing a corresponding increase in leakage current and therefore corresponding increases in overall current consumption and heat dissipation requirements. The backgate coupling can be reduced by increasing the device sizes, however, that consumes very expensive, precious area on the semiconductor die.
Referring now to FIG. 1E, the current waveforms 160A and 160B respectively, for the grounded gate keeper circuit and the feedback gate keeper circuit are shown. The current waveform 160A for the grounded gate keeper circuits 142A and 142B is shown slightly elevated (e.g., at about 80 u amp) as compared to the current waveform 160B for the feedback gate keeper circuits 142A′ and 142B′ (e.g., at about 0 u amp). The slightly elevated current flow in current waveform 160A is caused by noise on the ground potential. One main source for the noise on the ground potential is again generated by the NAND gate 122.
In view of the foregoing, there is a need for a system and method of maintaining the voltage on the local match lines while substantially reducing the leakage current experienced by the prior art keeper circuits 142A, 142B, 142A′ and 142B′.